In the packaging of integrated circuits, dies may be packaged onto a package substrate (sometimes known as a laminate substrate), which includes metal connections that may route electrical signals between opposite sides of the laminate substrate. The dies may be bonded onto one side of a laminate substrate using flip chip bonding, and a reflow is performed to melt the solder bumps that interconnect the dies and the laminate substrate. Laminate substrates may be used in package-on-package structures and system-in-package structures.
In a conventional packaging and testing process, a plurality of known-good-dies that is sawed from a wafer is first bonded on a package substrate strip, which comprises a plurality of package substrates therein. The bonding may be a flip chip bonding. Underfill is then dispensed into the gaps between the known-good-dies and the package substrates. Solder balls are also placed on the package substrate strip, and are reflowed. The package substrate strip is then separated into a plurality of units, wherein each of the resulting units has a known-good-die and a single package substrate.
A first function test is performed on the plurality of units to find failed units. Next, each of the plurality of units that passes the first function test is placed on a jig that has the size to fit one unit. An upper component stack may then be placed on the unit. The upper component stack may be a package that includes an additional die and additional package substrate.
Next, the jig, the unit, and the upper component stack go through a reflow process, so that the upper component stack is bonded with the unit to form a package. A second function test may then be performed on the resulting package to determine the quality of the resulting package.
With the increasing down scaling of integrated circuits, the units comprising the packages and the overlying dies also become increasing smaller. This requires that the size of the corresponding jig to be small. The small jigs are difficult to handle during the step of bonding the upper component stacks to the units. This results in a low throughput and possibly a low yield.